The present invention relates to methods for patterning substrates, such as reticles, masks or wafers, which reduce critical dimension variations, improving CD uniformity. In particular, it relates to tuning doses applied in passes of a multipass writing strategy to measurable characteristics of resists or radiation sensitive layers applied to the substrates. Particular writing strategies are described.
Semiconductor devices include multiple layers of structure. The structures are formed in numerous steps, including steps of applying resist, then exposing, developing and selectively removing the resist to from a pattern of exposed areas. The exposed areas may be etched to remove material or sputtered to add material. A critical part of forming the pattern in the resist is exposing it. Resist is exposed to an energy beam that changes its chemical properties.
One way of exposing the resist is with a stepper. The stepper uses a reticle, which typically includes a carefully prepared, transmissive quartz substrate overlaid by a non-transmissive or masking layer that is patterned with areas to be exposed and areas to be left unexposed. Patterning is an essential step in the preparation of reticles. Reticles are used to manufacture semiconductor and other devices, such as flat panel displays and television or monitor screens.
A spatial light modulator (SLM) comprises a number of modulator elements, which can be set in a desired way for forming a desired pattern. Reflective SLMs may be exposed to any kind of electromagnetic radiation, for example DUV or EUV for forming the desired pattern on the mask.
SLM writers disclosed in other patent applications, such as WO 01/18606, are related to raster scanning in the sense that it permits a bitmap pattern, but distinct by printing an entire frame of pattern in one flash instead of building the pattern from individual pixels.
The pattern on the reticle used to produce semiconductor devices is typically four times larger than that on a wafer being exposed. Historically, this reduction factor has meant that minimum feature dimensions in the reticles are less critical than the minimum feature dimensions on a surface of the semiconductor. However, a difference in criticality is much less than might be expected and will in the near future disappear.
Critical dimension uniformity (CD uniformity), as a percentage of the line width, is more exacting in the pattern on a reticle than in features on a surface of the wafer. CD uniformity refers to the minimization of variation of a single critical dimension at different points within the pattern. In other words, as the difference in actual dimension of features having the same critical dimension decreases within the pattern, CD uniformity increases. On the wafer, critical dimension uniformity of plus or minus 10 percent of the line width has historically been acceptable. In the error budget for the wafer line width, the mask has been allowed to contribute half of the critical dimension variation, or a variation of five percent of a line width. Other factors use the remaining error budget.
Critical dimension control is becoming more and more critical in the mask making industry as the exposure wavelength goes down. For laser pattern generators, the move from traditional DNQ/Novolak based towards DUV chemically amplified resist processing was initially troublesome. The relative long total exposure time of pattern generators in contrast to wafer steppers, in combination with thick quartz substrates with relatively low heat capacity, may result in reduced lithographic performance due to excessive diffusion of photogenerated acid. The photoresist polymer architecture play a large role in determining the acid diffusion characteristics and thereby also the image fidelity and resolution.
It is anticipated that requirements for critical dimension uniformity will tighten in time, particularly for masks. On the surface of the wafer, a critical dimension uniformity of plus or minus five percent of the line width will be required in the future. At the same time, the mask error enhancement factor is likely to increase due to more aggressive lithographic process trade-offs, such as tuning the lithographic process to optimize the manufacture of contact holes, transistors or other critical features in order to use feature sizes closer to the theoretical resolution limit. For masks, a critical dimension uniformity of plus or minus one percent of a line width or feature size is anticipated. At this rate, the tolerance for critical dimension errors on the mask will be smaller in absolute nanometers than it is on the surface of the wafer, despite the fact that the stepper takes advantage of a mask that is four times as large as the area on the wafer that is being exposed.
Thus, it is desirable to develop improved methods for patterning reticles or wafers, which will further reduce the critical dimension variation.